This application claims the priority of Korean Patent Application No. 2002-50836 filed on Aug. 27, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to the structure of a fuse bank of a semiconductor memory device for reducing the pitch of the fuse bank.
2. Description of the Related Art
After all manufacturing steps of semiconductor memory devices have been completed; the semiconductor memory devices are tested for determining to whether the devices operate normally or not by various testing methods using various test parameters. If a defective control circuit of control circuits of a semiconductor memory device has been discovered during testing of the semiconductor memory device, the semiconductor memory device becomes unusable. However, if a defective memory cell or memory cells of a semiconductor memory device has been discovered during testing of the semiconductor memory device, the defective memory cell can be replaced with a redundant memory cell and the semiconductor memory device can operate normally. Fuses are widely used in the semiconductor memory devices having a scheme that replaces the defective memory cell with a redundant memory cell.
In a case where a defective memory cell exists, fuses connected to the defective memory cell are opened so that a redundant memory cell, in which the fuses are open, is driven by information. Thus, the defective memory cell can be replaced with the redundant memory cell. A fuse bank including multiple fuses is embedded in a chip of a semiconductor memory device so that the fuse bank becomes an element of the semiconductor memory device.
Currently, a trend exists of reducing the size of fuses as well as other elements in semiconductor memory devices. However, the extent of the size reduction of the fuses is less than that of the size reduction of other elements. Therefore, the size of the fuses may be contrary to the trend of smaller semiconductor memory devices.
FIG. 1 illustrates a first example of the layout structure of a conventional fuse bank 100. The fuse bank 100 of FIG. 1 includes multiple fuses 110, 120, 130, and 140. The multiple fuses 110, 120, 130, and 140 are arranged to extend in the same direction and are be parallel to each other.
In FIG. 1, in a case where the fuse bank 100 includes n fuses, the lateral size of the fuse bank 100 is n×PF. Here, n is an integral number, and PF represents the pitch between the fuses. The pitch PF is a parameter that is affected by fuse equipment rather than the minimum feature size with respect to respective lot generation. Reducing the minimum feature size does not reduce the pitch. Thus, the fuse size can affect layouts of other elements of a semiconductor memory device.
In order to solve the above problem, there is proposed a layout of a fuse bank having a structure different from that of the fuse bank of the FIG. 1. FIG. 2 illustrates a second example of the layout structure of a conventional fuse bank. The layout structure of the fuse bank shown in FIG. 2 is disclosed in U.S. Pat. No. 6,215,715, entitled “Integrated circuit memories including fuses between a decoder and a memory array for disabling defective storage cells in the memory array” and issued on Apr. 10, 2001, and incorporated by reference herein.
The fuse bank 200 shown in FIG. 2 includes multiple fuses 210, 220, 230, and 240. The multiple fuses 210, 220, 230, and 240 are grouped together in the longitudinal direction to form a single fuse bank 200.
In FIG. 2, in a case where the fuse bank 200 includes n fuses, the lateral size of the fuse bank 200 is given by the following Equation (1):Lateral Size=(1.5n−2)×PL+2WL+LF  (1)In Equation (1), PL represents the pitch between connecting lines, WL represents the width of the connecting line, and LF represents the length of a laser fusing region.
As can be seen from Equation (1), the lateral size of the fuse bank has nothing to do with the pitch PF between the fuses. The lateral size of the fuse bank 200 can be reduced compared with that of the fuse bank 100 shown in the FIG. 1 by changing the layout of the fuse bank shown in FIG. 2.
However, the layout of the fuse bank 200 shown in FIG. 2 cannot be embodied on a single layer, because overlapped portions between the fuses exist, so two layers are required. Thus, a fuse bank layout that can be embodied on a single layer so as to reduce the size of the fuse bank is required.